A digital predistorter (DPD) is a current mainstream apparatus for power amplifier predistortion correction, and has been widely used in previous second-generation, third-generation, and fourth-generation communications technologies.
With continuous development of communications technologies, available bandwidths also keep increasing. To adapt to a larger bandwidth, a 2-fold bandwidth sampling manner is used for solving in the prior art. Specifically, a feedback signal with a bandwidth of four to five times larger than a signal bandwidth is sampled by using a high-speed analog-to-digital converter (ADC) and transmitted to a field programmable gate array (FPGA)/an application-specific integrated circuit (ASIC) by using a serializer/deserializer (SerDes). The FPGA/ASIC performs low-pass filtering to remove a specific stray signal, then performs 2-fold bandwidth signal extraction, and feeds back an extracted signal for preprocessing. After being phase-aligned, the signal is sent to a solving unit for solving, so as to meet a larger-bandwidth requirement.
However, in research of the communications technologies, a DPD feedback bandwidth of a future mobile communications technology, such as the fifth-generation mobile communications technology (5G), may reach 3 to 4 gigahertz (GHz). However, energy consumption of a prior-art ADC still cannot satisfy such an ultra-large bandwidth.